1. Field of the Invention
The present invention relates to a semiconductor memory device having the function of switching access to defective memory in a memory array to access to redundant memory provided in advance.
2. Description of the Related Art
In recent years, advances in semiconductor miniaturization technology have led to remarkable advances in the increase of capacity of semiconductor memories. On the other hand, however, a signal generated from a miniature memory cell becomes very weak, so the statistical probability of occurrence of cell defects accompanied with variations in the production process becomes high.
Defects of memory cells are generally dealt with by referring to a defect map describing addresses etc. of the defective cells for each repair unit. Conventionally, the defect map is programmed in fuses etc. provided inside the semiconductor memory. Defective cells and redundant cells are exchanged based on this defect map. Defective cells and redundant cells are frequently exchanged for entire large groups such as word line units and bit line units. However, many statistical cell defects explained above occur at random in small units. Therefore, too many fuses and redundant cells must be prepared with the method of using large repair units and not all of the defects can be repaired.
In order to deal with such a problem, the technique has been proposed of using a defect map stored in a nonvolatile memory etc. provided in the chip so as to reduce the repair units to the units of bits, bytes, and words.
For example, there is the technique of individually providing a data cell array, a redundant cell array, and a defect address memory portion. The defect address memory portion stores addresses of rows and columns for specifying defective cells in the data cell array. When one of the plurality of defect addresses stored in the defect address memory portion coincides with the input address, the redundant cell corresponding to the coinciding defect address is selected and accessed in place of the defective cell. Due to this, the defective cells in the data cell array are replaced by memory cells in the redundant cell array in units of bits.
However, when preparing a defect map common to the entire memory area in this way and trying to repair random defects based on this, it is necessary to scan all addresses stored in the defect address memory portion and repair the cells of the addresses coinciding with the input addresses. This does not become a major problem when there are few defects, but when a large amount of defects occur, it becomes necessary to mount a comparison circuit for each of the large number of defect addresses, so an enormous number of comparison circuits become necessary. Accordingly, this technique is not preferred both from the viewpoints of the occupied circuit area and the comparison and search time.
Contrary to this, the technique has also been proposed of dividing the memory area in accordance with the addresses and providing a defect map for repairing random defects for each divided section. Each defect map includes information for specifying the defective cells limited to the corresponding section. The defect map corresponding to the section of access target can be selected by decoding an input address. According to this technique, each defect map can be reduced in scale, so a reduction of the comparison circuit and a shortening of the delay time can be achieved.
For example, there is a technique of converting the input addresses to index parts and tag parts and dividing the memory area by using the index parts. According to this technique, there is provided a defect repair memory separately from the main memory. The defect repair memory stores the defect maps and provides redundancy memory cells. When an address is input to the memory device, the input address is converted to an index part and tag part, then the defect map corresponding to the index part is selected by decoding the index part and the selected defect map is read out from the defect repair memory. Then, the defective memory cell is specified by referring to the read defect map and the tag part.
Japanese Unexamined Patent Publication (Kokai) No. 11-120788 proposes a configuration providing redundant cells and the defect map storage cells as sets on the same rows in the memory array in addition to the data cells. In Japanese Unexamined Patent Publication (Kokai) No. 11-120788, one row in the memory array can be regarded as a memory region corresponding to the section or index part. When a row of the memory is selected according to a row address of the input address, the defect map corresponding to that row is simultaneously selected, and the defect location in the row is specified. By this, it becomes possible to repair random defects for each row.
Summarizing the problems to be solved by the invention, the repairing method of defective memory cells explained above is effective as a basic concept, but when applying it to an actual memory chip, there are the following disadvantages.
For example, in the technique of converting input addresses to index parts and tag parts, the conversion is only “performed so as to optimize the repair efficiency”. Namely, index parts can be physically linked with word line selection addresses of the defect repair memory, but the physical link between the defect repair memory and the main memory remains in an arbitrary state.
As a result, an access operation to the main memory and the defect repair memory are not related to each other and synchronized, but completely independently. Accordingly, whenever an address for accessing the main memory is input from the outside, the input address must be converted to an index part and a tag part, the word line of the defect repair memory corresponding to the index part must be selected, and the data must be read out from the defect repair memory by activating a sense amp circuit thereof.
On the other hand, when the main memory is for example a DRAM, the random access is carried out at a relatively low speed, but the random access and burst access of the CAS (column address strobe) performed after activating a word line are carried out at an extremely high speed. Further, the same high speed access is possible also in a relatively low speed flash memory etc. In general, the technique of selecting the row address and outputting data groups read out from the memory cells on the same word line to a latch circuit in parallel, then accessing the data groups of the latch circuit at a high speed according to the column address is used in various memories.
Accordingly, when using such a high-speed access mode, the word line is not selected in the main memory. On the other hand, in the defect repair memory, the index conversion, the row selection, the defect map reading, and the judgment of coincidence of the address and the map are executed by the usual routines. As a result, there is the disadvantage that the output from the defect repair memory and the comparison judgment following it are no longer in time for the access operation of the main memory.
In the technique of Japanese Unexamined Patent Publication (Kokai) No. 11-120788, the row addresses of the data memory cells and the index parts directly correspond, therefore when a row address is given, the data memory cell, the defect map storage cell, and the redundant memory cell connected to same row line become accessible simultaneously. Accordingly, it is also easy to handle the above high speed access mode.
In the technique according to Japanese Unexamined Patent Publication (Kokai) No. 11-120788, however, the memory groups (sets of the defect map storage cells and the redundant memory cells) are directly allocated to the word lines, therefore there is the disadvantage that wasteful memory groups not contributing to the repair of defects increase and the repair efficiency becomes low. Further, due to the restriction in chip area, the number of the memory groups which can be allocated to each word line by the present technique is expected to be no more than about one or two sets, therefore there also exists the disadvantage that repair becomes impossible when more than that many defective cells are included on the same word line.
Further, when using the technique explained above to repair defects before shipping, the write operation of data of the defect map etc. for specifying a defect location is very troublesome.
Namely, a large amount of defect locations must first be detected by a function test using various test patterns, the data must be once collected and stored at the outside of the memory device under test, then it must be written into a defect map storage device corresponding to each memory device. Such a defect repair process requires enormous time and cost. Further, when storing defect maps in the same chip, the write operation of the defect maps is completely different from the write operation of usual data. Accordingly, it becomes necessary to provide special I/O pins for the defect maps and to perform a special operation mode for transferring the detect maps.
Further, in this repairing method of memory defects, there also exists the disadvantage that defects occurring due to aging of devices etc. after shipping cannot be handled.